3. Datapath Functional Units

3์žฅ Datapath Functional Units ๊ฐœ์š”

ํ”„๋กœ์„ธ์„œ์˜ Datapath๋ฅผ ๊ตฌ์„ฑํ•˜๋Š” ์ฃผ์š” ๊ธฐ๋Šฅ ์œ ๋‹›(Functional Unit)๋“ค์„ ํ•™์Šตํ•œ๋‹ค. Shifter, Comparator, Multiplier, Divider, Counter ๋“ฑ ALU ๋‚ด๋ถ€์˜ ํ•ต์‹ฌ ๊ตฌ์„ฑ ์š”์†Œ์™€ ๊ทธ ์„ค๊ณ„ ๊ธฐ๋ฒ•์„ ๋‹ค๋ฃฌ๋‹ค.

Shifter (์‹œํ”„ํ„ฐ)

Shift ์—ฐ์‚ฐ์€ ๊ณฑ์…ˆยท๋‚˜๋ˆ—์…ˆ์˜ ๋น ๋ฅธ ๊ทผ์‚ฌ์™€ ๋น„ํŠธ ์กฐ์ž‘์— ํ•„์ˆ˜. ์ฃผ์š” ์ข…๋ฅ˜:

  • Logical shift (LSL, LSR): 0์œผ๋กœ ์ฑ„์›€
  • Arithmetic shift (ASL, ASR): sign bit ์œ ์ง€ (signed division)
  • Rotate (ROL, ROR): ์ˆœํ™˜
  • Rotate through carry: carry bit ํฌํ•จ ์ˆœํ™˜

Barrel Shifter

n-bit ์‹œํ”„ํ„ฐ๋ฅผ 1 cycle ๋‚ด์— ์ž„์˜ shift ํšŸ์ˆ˜๋กœ ์ฒ˜๋ฆฌ. ARM์˜ ํŠน์ง•์  ์œ ๋‹›.

  • MUX tree ๊ตฌ์กฐ: log n ๋‹จ๊ณ„
  • 8-bit, 16-bit, 32-bit โ€ฆ ๊ฐ ๋‹จ๊ณ„์—์„œ shift ๋˜๋Š” ํ†ต๊ณผ
  • Area: O(n log n), Delay: O(log n)

Shifter ์ข…๋ฅ˜ ๋ฐ Barrel

Comparator (๋น„๊ต๊ธฐ)

๋‘ ์ˆ˜ A, B๋ฅผ ๋น„๊ตํ•ด A=B, A>B, A<B๋ฅผ ํŒ์ •.

Equality Comparator

$A = B \iff \text{XNOR}(a_i, b_i) = 1 \text{ for all } i$

์ฆ‰ ๊ฐ bit XNOR โ†’ AND๋กœ ๊ฒฐํ•ฉ.

Magnitude Comparator

  • Cascaded: ์ƒ์œ„ bit๋ถ€ํ„ฐ ๋น„๊ต, ๊ฐ™์œผ๋ฉด ๋‹ค์Œ bit๋กœ
  • Parallel: ๊ฐ bit ์Œ ๋น„๊ต ํ›„ priority encoder

Comparator

Multiplier (๊ณฑ์…ˆ๊ธฐ)

Array Multiplier

๊ฐ partial product๋ฅผ ๋ณ‘๋ ฌ๋กœ ์ƒ์„ฑ ํ›„ adder tree๋กœ ํ•ฉ์‚ฐ:

   A3 A2 A1 A0
ร—  B3 B2 B1 B0
โ”€โ”€โ”€โ”€โ”€โ”€โ”€โ”€โ”€โ”€โ”€โ”€โ”€โ”€โ”€
partial products 4๊ฐœ
   โ†’  shift + add

์ง€์—ฐ O(n), ๋ฉด์  O(nยฒ).

Booth Encoding

Signed ๊ณฑ์…ˆ์—์„œ ์—ฐ์†๋œ 1 bit๋ฅผ ๋ฌถ์–ด partial product ์ˆ˜๋ฅผ ์ค„์ž„.

  • Booth-2 (radix-4): 3-bit์”ฉ ๋ฌถ์–ด partial product๊ฐ€ ์ ˆ๋ฐ˜
  • Booth-4 (radix-8): 4-bit์”ฉ ๋ฌถ์–ด partial product๊ฐ€ 1/3

Booth Multiplier

Wallace Tree Multiplier

Partial product๋“ค์„ CSA (Carry Save Adder)๋กœ ์ค„์ด๋Š” reduction tree:

  • Depth = $O(\log n)$
  • ์ตœ์ข… 2๊ฐœ์˜ ์ˆ˜๋ฅผ CPA๋กœ ํ•ฉ์‚ฐ
  • ํ˜„๋Œ€ CPU์˜ ์ •์ˆ˜ multiplier ํ‘œ์ค€

Wallace Tree

Dadda Tree

Wallace์™€ ์œ ์‚ฌํ•˜์ง€๋งŒ adder ๊ฐœ์ˆ˜๊ฐ€ ์•ฝ๊ฐ„ ์ ์Œ. ๋ฉด์  ๋” ํšจ์œจ์ .

Dadda Tree

Divider (๋‚˜๋ˆ—์…ˆ๊ธฐ)

๋‚˜๋ˆ—์…ˆ์€ ๊ณฑ์…ˆ๋ณด๋‹ค ํ›จ์”ฌ ๋ณต์žก.

Restoring Division

  • ๋บ„์…ˆ ํ›„ ๊ฒฐ๊ณผ๊ฐ€ ์Œ์ˆ˜๋ฉด ์›์ƒ ๋ณต๊ตฌ(restore)
  • n-bit division: n cycle

Non-Restoring Division

  • ์›์ƒ ๋ณต๊ตฌ ์—†์ด ๋ถ€ํ˜ธ์— ๋”ฐ๋ผ ๋‹ค์Œ ์—ฐ์‚ฐ ๊ฒฐ์ •
  • ๋” ๋น ๋ฆ„, ํ˜„๋Œ€ ์ผ๋ฐ˜์  ๊ตฌํ˜„

SRT Division

  • Redundant digit set (โˆ’2, โˆ’1, 0, +1, +2)
  • Radix-4, Radix-8 SRT divider โ†’ cycle ์ˆ˜ ๊ฐ์†Œ
  • Intel Pentium์˜ ์œ ๋ช…ํ•œ FDIV bug๊ฐ€ SRT lookup table ์˜ค๋ฅ˜

Divider

Counter

  • Binary counter: n-bit ripple counter
  • Synchronous counter: ๋ชจ๋“  flip-flop์— ๊ฐ™์€ clock โ†’ skew ์ ์Œ, high freq ๊ฐ€๋Šฅ
  • Johnson counter, Ring counter: ์‹œํ”„ํŠธ ๋ ˆ์ง€์Šคํ„ฐ ๊ธฐ๋ฐ˜

Counter

Multiplexer / Demultiplexer

  • 2:1 MUX y </u></strong></mark> sยทb + sฬ„ยทa (AOI gate)
  • n:1 MUX๋Š” log n ์„ ํƒ ์‹ ํ˜ธ
  • ๋Œ€๊ทœ๋ชจ MUX๋Š” tree ๊ตฌ์กฐ๋กœ ๋ถ„ํ•ด

MUX/DEMUX

Register File

  • ์—ฌ๋Ÿฌ ํฌํŠธ(multi-port)๋ฅผ ๊ฐ€์ง„ SRAM ๊ธฐ๋ฐ˜ ์ €์žฅ์†Œ
  • ์ผ๋ฐ˜์ ์ธ RISC: 2 read port + 1 write port
  • Out-of-order ํ”„๋กœ์„ธ์„œ: 8+ read, 4+ write port ๋“ฑ
  • Area๊ฐ€ port ์ˆ˜์˜ ์ œ๊ณฑ์— ๋น„๋ก€

Register File

Memory Arrays (SRAM/DRAM)

  • SRAM: 6T cell, ๋น ๋ฆ„ (0.5~1 ns), ๋น„์Œˆ, ํœ˜๋ฐœ์„ฑ
  • DRAM: 1T1C cell, ๋А๋ฆผ (์ˆ˜์‹ญ ns), ์‹ธ๊ณ  ์กฐ๋ฐ€
  • Cache์—๋Š” SRAM, Main memory์—๋Š” DRAM

Memory Arrays

์ •๋ฆฌ

Unit ์šฉ๋„ ์ฃผ์š” ๊ธฐ๋ฒ•
Shifter Shift/Rotate Barrel shifter (log n)
Comparator ๋น„๊ต Parallel prefix
Multiplier ๊ณฑ์…ˆ Booth + Wallace tree
Divider ๋‚˜๋ˆ—์…ˆ SRT (Radix-4/8)
Counter ๊ณ„์ˆ˜ Synchronous
MUX ์„ ํƒ Tree of 2:1
RegFile ์ €์žฅ Multi-port SRAM

ALU๋Š” ์ด functional unit๋“ค์ด ๊ฒฐํ•ฉ๋œ ๋ณตํ•ฉ ํšŒ๋กœ. Datapath ์„ฑ๋Šฅ์€ ์ด๋“ค์˜ latency์™€ throughput์˜ ์กฐํ•ฉ์œผ๋กœ ๊ฒฐ์ •๋œ๋‹ค.

๋น„์Šทํ•œ ๊ธ€ ์ถ”์ฒœ

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