컴퓨터 구조
2. Pipelining
5-stage Pipeline Processor, Hazard, Prediction
3. Memory Herachy
Memory Herachy, Temporal/Spatial Localities, Cache
4. Virtual Memory
Paging, Page Table, TLB
5. Storage and other I/O
Dependability, Register Map, Polling, Interrupt, DMA, RAID
6. Multiprocessor
Shared Memory Multiprocessor, Critical-section, Network
1. Introduction
Instraction Set Architecture