1. Introduction
1μ₯ Introduction β μ»΄ν¨ν° ꡬ쑰 κ°μ
μ»΄ν¨ν° ꡬ쑰(Computer Architecture) μμ μ λμ ννΈλ‘, μΆμ μλ£ν(ADT), λͺ λ Ήμ΄ μ§ν© ꡬ쑰(ISA), μμ§λμ΄λ§ λ°©λ²λ‘ , μ±λ₯ νκ° μ§νλ₯Ό μ 리νλ€.
Abstract Data Type (ADT)
ADTλ λ°μ΄ν° νμ μ λ 립μ (independent) μΌλ‘ μ μνλ λ°©μμ΄λ€. ꡬνκ³Ό λΆλ¦¬ν΄μ, κ°μ μ§ν©(state)κ³Ό κ°μ λν΄ μ μλ μ°μ°(operation)λ§ λͺ μνλ€.
A set of data values (state) and associated operations that are precisely specified independent of any particular implementation.
μμ: Stack
Stackμ λ€μκ³Ό κ°μ΄ μ μλλ€.
- State:
push, pop, topμ΄ κ°λ₯ν μ ν μλ£κ΅¬μ‘° - Operation:
push(x),x <mark class="highlight"><strong><u> pop(),x </u></strong></mark> top()
ADTλ₯Ό μ μν΄ λλ©΄ ꡬ체 ꡬν(λ°°μ΄, μ°κ²° 리μ€νΈ λ±)κ³Ό 무κ΄νκ² λ Όλ¦¬μ μΈ μΈν°νμ΄μ€λ‘ μ¬μ©ν μ μλ€.

Instruction Set Architecture (ISA)
ISAλ μννΈμ¨μ΄μ νλμ¨μ΄κ° λ§λλ κ³μ½(contract) μ΄λ€. νλ‘μΈμκ° μ΄ν΄ν μ μλ λͺ λ Ήμ΄μ μ§ν©, λ μ§μ€ν° ꡬμ±, μ£Όμ μ§μ λ°©μ λ±μ μ μνλ€.
μ£Όμ κ°μ
- Registers (λ²μ© λ μ§μ€ν°, PC λ±), Memory: νλ‘κ·Έλ¨κ³Ό λ°μ΄ν°κ° μ μ₯λλ 곡κ°
- λͺ¨λ λͺ λ Ήμ΄λ Before / Afterμ μν λ³νλ₯Ό μΌκΈ°νλ€.
μμ λͺ λ Ήμ΄ λμ
λ©λͺ¨λ¦¬μ (j 15), beq r0, r1, 20, sw r2, 0(r0), lw r2, 1(r0), add r0, r1, r2 κ°μ λͺ
λ Ήμ΄κ° μ μ₯λμ΄ μμ λ:
- beq r0, r1, 2: branch if equal.
r0 == r1μ΄λ©΄ PC + 2(offset), μλλ©΄ λ€μ λͺ λ Ή(24λ²μ§ instruction) μ€ν. - Jump j 15: 15λ²μ§λ‘ 무쑰건 μ ν, PCκ° 15λ‘ λ³κ²½λ¨.
μ΄μ²λΌ κ° λͺ λ Ήμ΄ μ€ν μ ν λ μ§μ€ν°μ λ©λͺ¨λ¦¬ μνλ₯Ό μ ννκ² κΈ°μ νλ κ²μ΄ ISAμ μν μ΄λ€.
Engineering Methodology (Hennessy & Patterson)
The discipline of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data flow and controls, the logical design, and the physical implementation. β Amdahl, Blaauw, and Brooks, 1964
λ κ°μ§ ν©κΈ κ·μΉ
- Rule 1 β Identify and optimize the common case: νν λ°μνλ κ²½μ°μ λν΄μ λΉ λ₯΄κ² λ§λ€μ΄μΌ ν¨
- Rule 2 β Make the rare case correct and reasonably fast: μμ£Ό λ°μνμ§ μλ κ²½μ°μ λν΄μλ μλν μ μκΈ°λ§ νλ©΄ λ¨
μ¦ μμ£Ό μ°λ κ²½λ‘(common path)μ μ΅μ ν μμ°μ μκ³ , μμΈ μ²λ¦¬λ μ νμ±λ§ 보μ₯νμλ μ² ν.
Correctness Criteria
μ€κ³λ μμ€ν μ΄ μ¬λ°λ₯΄κ² ꡬνλμλμ§ νμΈνλ κΈ°μ€. μ±λ₯ μ΅μ ν μ΄μ μ λ°λμ λ§μ‘±μμΌμΌ ν 쑰건.
Performance Evaluation Methods
Performance Types
- Time κ΄μ
- Response time β μμ² ν μλ΅κΉμ§ μκ°
- Execution time β νλ‘κ·Έλ¨ μ€νμ κ±Έλ¦° μκ°
- Latency β κ°λ³ μ°μ° μ§μ°
- Rate κ΄μ (μκ°λΉ νλ μΌμ μ)
- Throughput: MIPS, MFLOPS
- Bandwidth: Mbps
- Ratio κ΄μ
- Relative performance β μμ€ν κ° μλ μ±λ₯ λΉκ΅ (time, rate λͺ¨λ κΈ°μ€ κ°λ₯)
Design Techniques
μ»΄ν¨ν° μμ€ν μ μ 체 μ€κ³λ μλ λ€ κ°μ ν° λΈλ‘μΌλ‘ λλλ€.
- Processor (I-cache, D-cache, Unified cache ν¬ν¨)
- Memory Hierarchy (κ³μΈ΅λ³ λ©λͺ¨λ¦¬)
- Interconnection Network
- Input/Output and Storage
μ΄ λΈλ‘λ€μ μ΅μ ννκΈ° μν λν κΈ°λ²:
- Sequential execution / Pipelined execution β μμ°¨ / νμ΄νλΌμΈ μ€ν
- Out-of-order execution / Speculative execution β λΉμμ°¨, ν¬κΈ°μ μ€ν (instructionμ μΆνλ κ²)
- Cache Design β I/D-cache, Unified cache
- Cache Coherence, Synchronization, Interconnection network β λ©ν° νλ‘μΈμ νκ²½ μ΅μ ν
β μμΌλ‘μ μ₯μμ Pipelining (2μ₯), Memory Hierarchy (3μ₯), Virtual Memory (4μ₯), Storage/IO (5μ₯), Multiprocessor (6μ₯) λ₯Ό νλμ© κΉμ΄ μκ² λ€λ£¬λ€.

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