1. Introduction

1μž₯ Introduction β€” 컴퓨터 ꡬ쑰 κ°œμš”

컴퓨터 ꡬ쑰(Computer Architecture) μˆ˜μ—…μ˜ λ„μž… 파트둜, 좔상 μžλ£Œν˜•(ADT), λͺ…λ Ήμ–΄ μ§‘ν•© ꡬ쑰(ISA), μ—”μ§€λ‹ˆμ–΄λ§ 방법둠, μ„±λŠ₯ 평가 μ§€ν‘œλ₯Ό μ •λ¦¬ν–ˆλ‹€.

Abstract Data Type (ADT)

ADTλŠ” 데이터 νƒ€μž…μ„ 독립적(independent) 으둜 μ •μ˜ν•˜λŠ” 방식이닀. κ΅¬ν˜„κ³Ό λΆ„λ¦¬ν•΄μ„œ, κ°’μ˜ μ§‘ν•©(state)κ³Ό 값에 λŒ€ν•΄ μ •μ˜λœ μ—°μ‚°(operation)만 λͺ…μ‹œν•œλ‹€.

A set of data values (state) and associated operations that are precisely specified independent of any particular implementation.

μ˜ˆμ‹œ: Stack

Stack은 λ‹€μŒκ³Ό 같이 μ •μ˜λœλ‹€.

  • State: push, pop, top이 κ°€λŠ₯ν•œ μ„ ν˜• 자료ꡬ쑰
  • Operation: push(x), x <mark class="highlight"><strong><u> pop(), x </u></strong></mark> top()

ADTλ₯Ό μ •μ˜ν•΄ 두면 ꡬ체 κ΅¬ν˜„(λ°°μ—΄, μ—°κ²° 리슀트 λ“±)κ³Ό λ¬΄κ΄€ν•˜κ²Œ 논리적인 μΈν„°νŽ˜μ΄μŠ€λ‘œ μ‚¬μš©ν•  수 μžˆλ‹€.

ADT와 ISA κ°œμš”

Instruction Set Architecture (ISA)

ISAλŠ” μ†Œν”„νŠΈμ›¨μ–΄μ™€ ν•˜λ“œμ›¨μ–΄κ°€ λ§Œλ‚˜λŠ” 계약(contract) 이닀. ν”„λ‘œμ„Έμ„œκ°€ 이해할 수 μžˆλŠ” λͺ…λ Ήμ–΄μ˜ μ§‘ν•©, λ ˆμ§€μŠ€ν„° ꡬ성, μ£Όμ†Œ μ§€μ • 방식 등을 μ •μ˜ν•œλ‹€.

μ£Όμš” κ°€μ •

  • Registers (λ²”μš© λ ˆμ§€μŠ€ν„°, PC λ“±), Memory: ν”„λ‘œκ·Έλž¨κ³Ό 데이터가 μ €μž₯λ˜λŠ” 곡간
  • λͺ¨λ“  λͺ…λ Ήμ–΄λŠ” Before / After의 μƒνƒœ λ³€ν™”λ₯Ό μ•ΌκΈ°ν•œλ‹€.

μ˜ˆμ‹œ λͺ…λ Ήμ–΄ λ™μž‘

λ©”λͺ¨λ¦¬μ— (j 15), beq r0, r1, 20, sw r2, 0(r0), lw r2, 1(r0), add r0, r1, r2 같은 λͺ…λ Ήμ–΄κ°€ μ €μž₯λ˜μ–΄ μžˆμ„ λ•Œ:

  • beq r0, r1, 2: branch if equal. r0 == r1이면 PC + 2(offset), μ•„λ‹ˆλ©΄ λ‹€μŒ λͺ…λ Ή(24λ²ˆμ§€ instruction) μ‹€ν–‰.
  • Jump j 15: 15λ²ˆμ§€λ‘œ 무쑰건 점프, PCκ°€ 15둜 변경됨.

이처럼 각 λͺ…λ Ήμ–΄ μ‹€ν–‰ μ „ν›„ λ ˆμ§€μŠ€ν„°μ™€ λ©”λͺ¨λ¦¬ μƒνƒœλ₯Ό μ •ν™•ν•˜κ²Œ κΈ°μˆ ν•˜λŠ” 것이 ISA의 역할이닀.

Engineering Methodology (Hennessy & Patterson)

The discipline of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data flow and controls, the logical design, and the physical implementation. β€” Amdahl, Blaauw, and Brooks, 1964

두 κ°€μ§€ ν™©κΈˆ κ·œμΉ™

  • Rule 1 β€” Identify and optimize the common case: ν”νžˆ λ°œμƒν•˜λŠ” κ²½μš°μ— λŒ€ν•΄μ„œ λΉ λ₯΄κ²Œ λ§Œλ“€μ–΄μ•Ό 함
  • Rule 2 β€” Make the rare case correct and reasonably fast: 자주 λ°œμƒν•˜μ§€ μ•ŠλŠ” κ²½μš°μ— λŒ€ν•΄μ„œλŠ” μž‘λ™ν•  수 있기만 ν•˜λ©΄ 됨

즉 자주 μ“°λŠ” 경둜(common path)에 μ΅œμ ν™” μ˜ˆμ‚°μ„ 쏟고, μ˜ˆμ™Έ μ²˜λ¦¬λŠ” μ •ν™•μ„±λ§Œ 보μž₯ν•˜μžλŠ” μ² ν•™.

Correctness Criteria

μ„€κ³„λœ μ‹œμŠ€ν…œμ΄ μ˜¬λ°”λ₯΄κ²Œ κ΅¬ν˜„λ˜μ—ˆλŠ”μ§€ ν™•μΈν•˜λŠ” κΈ°μ€€. μ„±λŠ₯ μ΅œμ ν™” 이전에 λ°˜λ“œμ‹œ λ§Œμ‘±μ‹œμΌœμ•Ό ν•  쑰건.

Performance Evaluation Methods

Performance Types

  • Time 관점
  • Response time β€” μš”μ²­ ν›„ μ‘λ‹΅κΉŒμ§€ μ‹œκ°„
  • Execution time β€” ν”„λ‘œκ·Έλž¨ 싀행에 κ±Έλ¦° μ‹œκ°„
  • Latency β€” κ°œλ³„ μ—°μ‚° μ§€μ—°
  • Rate 관점 (μ‹œκ°„λ‹Ή ν•˜λŠ” 일의 μ–‘)
  • Throughput: MIPS, MFLOPS
  • Bandwidth: Mbps
  • Ratio 관점
  • Relative performance β€” μ‹œμŠ€ν…œ κ°„ μƒλŒ€ μ„±λŠ₯ 비ꡐ (time, rate λͺ¨λ‘ κΈ°μ€€ κ°€λŠ₯)

Design Techniques

컴퓨터 μ‹œμŠ€ν…œμ˜ 전체 μ„€κ³„λŠ” μ•„λž˜ λ„€ 개의 큰 λΈ”λ‘μœΌλ‘œ λ‚˜λ‰œλ‹€.

  • Processor (I-cache, D-cache, Unified cache 포함)
  • Memory Hierarchy (계측별 λ©”λͺ¨λ¦¬)
  • Interconnection Network
  • Input/Output and Storage

이 블둝듀을 μ΅œμ ν™”ν•˜κΈ° μœ„ν•œ λŒ€ν‘œ 기법:

  • Sequential execution / Pipelined execution β€” 순차 / νŒŒμ΄ν”„λΌμΈ μ‹€ν–‰
  • Out-of-order execution / Speculative execution β€” λΉ„μˆœμ°¨, 투기적 μ‹€ν–‰ (instruction을 μΆ•ν•˜λŠ” 것)
  • Cache Design β€” I/D-cache, Unified cache
  • Cache Coherence, Synchronization, Interconnection network β€” λ©€ν‹° ν”„λ‘œμ„Έμ„œ ν™˜κ²½ μ΅œμ ν™”

β†’ μ•žμœΌλ‘œμ˜ μž₯μ—μ„œ Pipelining (2μž₯), Memory Hierarchy (3μž₯), Virtual Memory (4μž₯), Storage/IO (5μž₯), Multiprocessor (6μž₯) λ₯Ό ν•˜λ‚˜μ”© 깊이 있게 닀룬닀.

Engineering 방법둠 및 섀계 기법

λΉ„μŠ·ν•œ κΈ€ μΆ”μ²œ

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