1. Introduction

1์žฅ Introduction โ€” ARM๊ณผ ์ž„๋ฒ ๋””๋“œ ์‹œ์Šคํ…œ ๊ฐœ์š”

์ž„๋ฒ ๋””๋“œ ์‹œ์Šคํ…œ(Embedded System) ์€ ํŠน์ •ํ•œ ๋ชฉ์ ๊ณผ ์–ดํ”Œ๋ฆฌ์ผ€์ด์…˜์„ ์œ„ํ•ด์„œ ํ•˜๋“œ์›จ์–ด๋‚˜ ์†Œํ”„ํŠธ์›จ์–ด๋ฅผ ์ตœ์ ํ™”์‹œํ‚จ ์‹œ์Šคํ…œ์ด๋‹ค. ARM์€ ์ž„๋ฒ ๋””๋“œ ์‹œ์Šคํ…œ์—์„œ ๊ฐ€์žฅ ์œ ๋ช…ํ•œ ํ”„๋กœ์„ธ์„œ๋กœ, ๋‚ฎ์€ ์ „๋ ฅ ์†Œ๋น„, ์ž‘์€ ๋‹ค์ด ์‚ฌ์ด์ฆˆ, ๋†’์€ ์„ฑ๋Šฅ์„ ํŠน์ง•์œผ๋กœ ํ•œ๋‹ค.

Data Sizes and Instruction Sets

ARM์€ ์—ฌ๋Ÿฌ ์„ธ๋Œ€๋ฅผ ๊ฑฐ์น˜๋ฉฐ ๋‹ค์–‘ํ•œ ๋ฐ์ดํ„ฐ ํฌ๊ธฐ์™€ ๋ช…๋ น์–ด ์ง‘ํ•ฉ์„ ์ง€์›ํ•œ๋‹ค.

  • ARMv4 ์ด์ „: 32-bit instruction ์œ„์ฃผ
  • ARMv4 ์ดํ›„: Thumb instruction set ๋„์ž…
  • ๊ธฐ์กด 32-bit ARM instruction + 16-bit Thumb instruction ๋™์‹œ ์ง€์›
  • Short physical registers, virtual address, physical address ๋“ฑ ์„ค๊ณ„ ์š”์†Œ ์ •์˜

ARM๊ณผ Thumb Instruction

  • ARM instruction: 32-bit, full instruction set. Short physical registers, virtual address, physical address ๋“ฑ ์‚ฌ์šฉ
  • Thumb instruction: 16-bit, ARM์˜ ์ถ•์•ฝํŒ. ์ฝ”๋“œ ํฌ๊ธฐ ์ ˆ๊ฐ์„ ์œ„ํ•ด ๋„์ž…๋˜์–ด ๋ฉ”๋ชจ๋ฆฌ๊ฐ€ ์ž‘์€ ์ž„๋ฒ ๋””๋“œ ํ™˜๊ฒฝ์—์„œ ์œ ๋ฆฌ

Instruction Sets

ARM Instruction Set

  • 32-bit fixed-length instruction
  • ๊ฐ๊ฐ์˜ Instruction์€ ๊ฐ™์€ ์‹œ๊ฐ„์— ์ˆ˜ํ–‰ ๊ฐ€๋Šฅ (RISC ํŠน์„ฑ)
  • ํŒŒ์ดํ”„๋ผ์ธ์ด ํšจ์œจ์ ์œผ๋กœ ๋™์ž‘

Thumb Instruction Set

Thumb instruction set์€ ARM์˜ 32-bit instruction์„ 16-bit๋กœ ์••์ถ•ํ•œ ๊ฒƒ.

  • Variable-length instruction: 16-bit์ด๊ธฐ ๋•Œ๋ฌธ์— ARM๊ณผ ํ˜ผ์šฉ ๊ฐ€๋Šฅ
  • ์ฝ”๋“œ ํฌ๊ธฐ๊ฐ€ ์ž‘์•„์ง€์ง€๋งŒ, ์ผ๋ถ€ instruction์€ ๋ณต์žกํ•œ ์—ฐ์‚ฐ ์ˆ˜ํ–‰ ์‹œ ์—ฌ๋Ÿฌ cycle ํ•„์š”
  • ARM์€ Thumb 2๋กœ ๋„˜์–ด๊ฐ€๋ฉด์„œ 16/32-bit Thumb instruction์„ ์ง€์›ํ•˜๋ฉฐ ๊ฐœ์„ ๋จ

๊ธฐ๋ณธ ํŠน์„ฑ

  • Thumb instruction์ด ์ถ”๊ฐ€๋œ ์ด์œ : ์ž„๋ฒ ๋””๋“œ ํ™˜๊ฒฝ์—์„œ ๋ฉ”๋ชจ๋ฆฌ ์šฉ๋Ÿ‰์ด ์ž‘๊ธฐ ๋•Œ๋ฌธ์— ์ฝ”๋“œ ๊ณต๊ฐ„ ์ ˆ๊ฐ ํ•„์š”
  • ์†๋„๋Š” ARM instruction๋ณด๋‹ค ์กฐ๊ธˆ ๋‚ฎ์ง€๋งŒ, ๋ฉ”๋ชจ๋ฆฌ access๊ฐ€ ์ ์–ด์ ธ ์ „์ฒด ์„ฑ๋Šฅ์€ ํ–ฅ์ƒ๋  ์ˆ˜ ์žˆ์Œ

ARM/Thumb Instruction Set

Summary

  • ARM์€ ์ž„๋ฒ ๋””๋“œ ์‹œ์Šคํ…œ์—์„œ ๊ฐ€์žฅ ์œ ๋ช…ํ•œ ํ”„๋กœ์„ธ์„œ (ํŠน์ •ํ•œ ๋ชฉ์ ๊ณผ ์–ดํ”Œ๋ฆฌ์ผ€์ด์…˜์„ ์œ„ํ•ด ํ•˜๋“œ์›จ์–ด๋‚˜ ์†Œํ”„ํŠธ์›จ์–ด๋ฅผ ์ตœ์ ํ™”์‹œํ‚จ ์‹œ์Šคํ…œ)
  • ARM์€ RISC์˜ ํ‘œํ˜„์ด ๋˜์–ด๊ฐ€๊ณ  ์žˆ์Œ (์ž‘์€ ์‚ฌ์ด์ฆˆ, ๊ณ ์„ฑ๋Šฅ) vs. ์ธํ…” CISC (๋ฉ”๋ชจ๋ฆฌ๋ฅผ ์ž‘๊ฒŒ Access, Cache ์ดํ›„ ์ฆ๊ฐ€, ํŒŒ์ดํ”„๋ผ์ธ โ†“, ๋ช…๋ น์–ด๋„ ๋ณต์žก)
  • RISC (Reduced Instruction Set Computer): ๋‹จ์ˆœํ•˜๊ณ  ๋น ๋ฅธ ๋ช…๋ น์–ด
  • CISC (Complex Instruction Set Computer): ๋ณต์žกํ•œ ๋ช…๋ น์–ด, ๋” ๋งŽ์€ ํด๋ก cycle
  • Pipelining์ด ํ•„์ˆ˜์  (RISC์˜ ๊ธฐ๋ณธ์ ์ธ ํ…Œํฌ๋‹‰)
  • Instruction์„ ์ค‘์ฒฉํ•ด์„œ ๋™์‹œ์— ์ˆ˜ํ–‰ ๊ฐ€๋Šฅ, ํ•ด์ €๋“œ์˜ ์œ„ํ—˜์ด ์žˆ์Œ
  • ์ €์ „๋ ฅ์€ ํ•„์ˆ˜์  (ํŒŒ์›Œ vs. ์„ฑ๋Šฅ) โ†’ ๊ณต์ • ๊ฐœ๋ฐœ๋กœ leakage power ๊ฐ์†Œ ์ค‘์š”

ARM์˜ ํŠน์ง• ์š”์•ฝ

๋น„์Šทํ•œ ๊ธ€ ์ถ”์ฒœ

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