4. ARM Assembly Programming

4์žฅ ARM Assembly Programming ๊ฐœ์š”

ARM Assembly์˜ ๊ธฐ๋ณธ ๋ฌธ๋ฒ•๊ณผ ์‹ค์ œ ํ”„๋กœ๊ทธ๋ž˜๋ฐ์— ํ•„์š”ํ•œ ๋ช…๋ น์–ด, Immediate operation, Shifted Register Operands, Addressing Mode, Branch, Subroutine ๋“ฑ์„ ๋‹ค๋ฃฌ๋‹ค.

ARM Assembly ๊ธฐ๋ณธ ๊ตฌ์กฐ

[label] instruction [operands] [; comment]
  • Label: ์ฝ”๋“œ ๋ผ์ธ์— ์ด๋ฆ„์„ ๋ถ™์—ฌ jump target ์ง€์ •
  • Instruction: ARM mnemonic
  • Operands: ์ฃผ๋กœ register, immediate, label
  • Comment: ;๋กœ ์‹œ์ž‘

General Features

ARM Assembly์˜ ์ผ๋ฐ˜์ ์ธ ํŠน์ง•.

  • Arithmetic, Logical Operations: ADD, SUB, AND, ORR ๋“ฑ
  • ALU ์—ฐ์‚ฐ์€ register-to-register, ์ตœ๋Œ€ 3 operand

Suffixed Format

<instruction>{S}{cond} ํ˜•ํƒœ. S๋Š” flag update, cond๋Š” conditional execution.

์˜ˆ: ADDEQS r0, r1, r2 โ†’ EQ ์กฐ๊ฑด์ด ์ฐธ์ผ ๋•Œ๋งŒ ์‹คํ–‰, flag ๊ฐฑ์‹ 

Simple Register Operands

  • ADD r0, r1, r2: r0 = r1 + r2
  • 3 operand ๋˜๋Š” 2 operand form

Arithmetic Operation

  • ADD, SUB, RSB (reverse subtract), ADC (add with carry), SBC, RSC
  • ์™œ RSB๊ฐ€ ํ•„์š”ํ•œ์ง€: ARM์€ r0 <mark class="highlight"><strong><u> r1 - r2์™€ r0 </u></strong></mark> r2 - r1์„ immediate ํ™œ์šฉ ์‹œ ๋ชจ๋‘ ์œ ์šฉ

Bitwise Logical Operation

  • AND, ORR, EOR (XOR), BIC (bit clear = AND NOT)
  • ์˜ˆ: BIC r0, r1, #0xFF โ†’ r1์˜ ํ•˜์œ„ 8bit๋ฅผ ๋ชจ๋‘ 0์œผ๋กœ

Bit Shift Operation

  • MOV, MVN (move NOT), shift ํฌํ•จ ๊ฐ€๋Šฅ

Comparison Operation (No destination)

  • CMP (compare SUB, flag๋งŒ), CMN (compare negative ADD, flag๋งŒ)
  • TST (test AND, flag๋งŒ), TEQ (test equal EOR, flag๋งŒ)

ARM Assembly ๊ฐœ์š” ๋ฐ Register/Arithmetic Operations

Immediate Operation

ํ•˜๋‚˜์˜ operand (๋’ค์˜ operand)๋Š” ์ƒ์ˆ˜๋กœ ์˜ฌ ์ˆ˜ ์žˆ์Œ (#์„ ์ด์šฉ).

์˜ˆ: ADD r3, r3, #1, ADD r8, r7, #&ff

์ƒ์ˆ˜ ์„ค์ • ์กฐ๊ฑด

ARM instruction์€ 32-bit ๊ณ ์ •์ด๋ผ immediate์—๋Š” 12 bit ๊ณต๊ฐ„. Cond | opcode | 12bit(rn) | 4bit(r1) | 4bit | 4bit 12bit.

  • ์ƒ์ˆ˜ ๋ฒ”์œ„: $0 \sim 2^{12} - 1$๊นŒ์ง€๋งŒ ํ‘œํ˜„ ๊ฐ€๋Šฅ
  • 12-bit์„ ๋” ์ž˜ ์‚ฌ์šฉํ•˜๊ธฐ ์œ„ํ•ด (๋งŽ์ด ์‚ฌ์šฉํ•˜๋Š” bit๋งŒ) shift์‹œ์ผœ ์‚ฌ์šฉ
  • $(0 \sim 2^8 - 1) \times 2^{2n} = (0 \sim 2^8 - 1) \ll 2n$ โ€” 8bit ร— non 4bit shift
  • 4bit์„ ์‚ฌ์šฉํ•ด์„œ $0 \leq n \leq 12$๊นŒ์ง€ ํ‘œํ˜„
  • Encodeํ•  ์ˆ˜ ์—†๋Š” ๊ฐ’์ด๋ฉด Assembler๊ฐ€ ๊ฒฝ๊ณ 

Shifted Register Operands

3 or 4 address instruction: 2๋ฒˆ์งธ reg operand๋ฅผ shiftํ•  ์ˆ˜ ์žˆ๊ธฐ์— 4 address I.

์˜ˆ: ADD r3, r2, r1, LSL #3 โ†’ r3 = r2 + 8*r1

  • <<3์€ 8์„ ๊ณฑํ•ด์ค€ ๊ฒƒ๊ณผ ๊ฐ™์Œ
  • ๊ณฑ์…ˆ๊ธฐ๋Š” 1 clock ์•ˆ์— ์ˆ˜ํ–‰๋˜์ง€ ์•Š๋Š” ๊ฒฝ์šฐ๊ฐ€ ๋งŽ์Œ โ†’ shift ์—ฐ์‚ฐ์„ ์ˆ˜ํ–‰ํ•˜๋ฉด ๊ณฑ์…ˆ๋„ 1 clock์— ์ˆ˜ํ–‰ ๊ฐ€๋Šฅ (ARM์˜ ํŠน์ง•, ๋‹ค๋ฅธ ํ”„๋กœ์„ธ์„œ๋Š” ๋ณ„๋„ ์ž์›)

reg๋กœ ์‚ฌ์šฉ๋„ ๊ฐ€๋Šฅ. ์˜ˆ: ADD r5, r5, r3, LSL r2 โ†’ r5 = r5 + r3 * 2^r2

Shift Mnemonics

  • LSL(R): Logical shift left (Right)
  • ASL(R): Arithmetic shift left (Right) โ†’ ASR์˜ ๊ฒฝ์šฐ Sign-extension์„ ํ•ด์ค˜ LSR๊ณผ ๊ฒฐ๊ณผ๊ฐ€ ๋‹ค๋ฆ„
  • ROR: Rotate right
  • RRX: Carry๋„ ํ•ฉ์ณ์„œ Rotate

Immediate Operation ๋ฐ Shifted Register

Setting Condition Code

๊ฐ Data processing I์— condition code suffix๋ฅผ ์“ฐ๋ฉด:

  • S suffix condition code ๊ฒฐ๊ณผ๊ฐ€ CPSR์— ๋ฐ˜์˜

Multiplication

  • MUL r0, r1, r2 โ†’ r0 = (r1 * r2)[31:0] (ํ•˜์œ„ 32bit๋งŒ)
  • MLA r0, r1, r2, r3 โ†’ r0 = (r1 * r2 + r3)[31:0] (multiply accumulate)
  • Multiply and accumulate: MLA r0, r1, r2, r3; MLAS (condition code ๋ฐ˜์˜)

Data-Transfer Instruction (Load/Store)

Register๋ฅผ ๋ฉ”๋ชจ๋ฆฌ์— load/store.

  • Single register load/store (LDR, STR): byte/halfword/word
  • Multiple register load/store (LDM, STM): block transfer

Register Indirect Addressing

์˜ˆ: LDR r0, [r1] โ†’ r0 <mark class="highlight"><strong><u> mem[r1], STR r0, [r1] โ†’ mem[r1] </u></strong></mark> r0

Initializing an Address Pointer

Load from: Load from label; ํ˜„์žฌ PC ๊ธฐ์ค€.

Condition Code, Multiplication, Data Transfer

Pointing label 1 and label 2

๋ฉ”๋ชจ๋ฆฌ ์ƒ์˜ labeled data์— pointer ์„ค์ • ์˜ˆ์ œ.

Single Register Load/Store I

Base with offset, pre/post indexed auto-increment ์˜ˆ์ œ๋ฅผ ํ†ตํ•ด ๊ตฌ์กฐ ์ดํ•ด.

Base + Offset Addressing

  • Pre-indexed addressing: LDR r1, [r0, #4] โ†’ r1 = mem[r0 + 4], r0 ๋ณ€๊ฒฝ X
  • Pre-indexed with writeback: LDR r1, [r0, #4]! โ†’ r1 <mark class="highlight"><strong><u> mem[r0 + 4], r0 </u></strong></mark> r0 + 4
  • Post-indexed: LDR r1, [r0], #4 โ†’ r1 <mark class="highlight"><strong><u> mem[r0], r0 </u></strong></mark> r0 + 4

Base+Offset Addressing ์˜ˆ์ œ

Multiple Register Data Transfer

์—ฌ๋Ÿฌ register๋ฅผ ํ•œ ๋ฒˆ์— load/store.

  • LDM (Load Multiple): LDMIA r0!, {r1-r3} โ†’ r1 <mark class="highlight"><strong><u> mem[r0], r2 </u></strong></mark> mem[r0+4], r3 <mark class="highlight"><strong><u> mem[r0+8], r0 </u></strong></mark> r0 + 12
  • STM (Store Multiple): ๋™์ผํ•˜๊ฒŒ ์ €์žฅ

Addressing Mode

  • IA (Increment After), IB (Increment Before), DA (Decrement After), DB (Decrement Before)
  • Stack์—์„œ ์“ฐ์ด๋Š” ๊ฒฝ์šฐ: FD (Full Descending), FA, ED, EA

Stack Addressing

  • Full stack (F): SP๊ฐ€ ๋งˆ์ง€๋ง‰ ์ €์žฅ๋œ ๊ฐ’์„ ๊ฐ€๋ฆฌํ‚ด
  • Descending stack (D): stack์ด ๋‚ฎ์€ ์ฃผ์†Œ๋กœ ์„ฑ์žฅ

ARM์€ ํ‘œ์ค€ Full Descending (FD) stack์„ ์‚ฌ์šฉ.

Block Copy Addressing

LDMIA/STMIA ์กฐํ•ฉ์œผ๋กœ ๋ฉ”๋ชจ๋ฆฌ block์„ ํšจ์œจ์ ์œผ๋กœ ๋ณต์‚ฌ.

Multiple Register Transfer ๋ฐ Stack

Block Copy Addressing Usage

  • LDMIA r8!, {r0-r3}: Load Multiple Increment After (4๊ฐœ ๋ ˆ์ง€์Šคํ„ฐ์— load, r8 update)
  • STMIA r9!, {r0-r3}: Store Multiple Increment After
  • โ†’ Block copy loop ๊ตฌ์กฐ์˜ ํ•ต์‹ฌ

๋น„์Šทํ•˜๊ฒŒ:

  • Full descending stack (STMFD/LDMFD): Stack push/pop
  • Descending stack, full-empty check

Branch Instruction

  • Unconditional jump: B label, BL label
  • Conditional jump: BEQ label, BNE label ๋“ฑ

PC relative addressing, offset 24-bit โ†’ ยฑ32MB ๋ฒ”์œ„ jump ๊ฐ€๋Šฅ.

Block Copy ๋ฐ Branch

Branch Condition

Branch Interpretation Flag state
BEQ Equal Z=1
BNE Not equal Z=0
BCS/BHS Carry set/unsigned high or same C=1
BCC/BLO Carry clear/unsigned low C=0
BMI Minus N=1
BPL Plus N=0
BVS Overflow set V=1
BVC Overflow clear V=0
BHI Higher (unsigned) C=1 AND Z=0
BLS Lower or same (unsigned) C=0 OR Z=1
BGE Greater or equal (signed) N=V
BLT Less than (signed) Nโ‰ V
BGT Greater than (signed) Z=0 AND N=V
BLE Less or equal (signed) Z=1 OR Nโ‰ V

Conditional Execution

์ผ๋ฐ˜์ ์ธ ๋ฐฉ๋ฒ•์œผ๋กœ branch ํ•  ๋•Œ conditional execution์„ ์‚ฌ์šฉํ•œ๋‹ค.

if (r1 > r0) { r0 <mark class="highlight"><strong><u> r0 - 2; } else { r0 </u></strong></mark> r0 + 2; }

์ผ๋ฐ˜์  branch ์‚ฌ์šฉ ์‹œ:

CMP r0, r1
BGT ELSE
SUB r0, r0, #2
B END
ELSE:
ADD r0, r0, #2
END:

Conditional execution ์‚ฌ์šฉ ์‹œ:

CMP r0, r1
SUBLE r0, r0, #2   ; condition์ด LE์ด๋ฉด ์‹คํ–‰
ADDGT r0, r0, #2   ; condition์ด GT์ด๋ฉด ์‹คํ–‰

โ†’ Branch๋ฅผ ์—†์•  pipeline์ด ํšจ์œจ์ . ARM ํŠน์œ ์˜ ๊ฐ•๋ ฅํ•œ ๊ธฐ๋Šฅ.

Branch Condition ๋ฐ Conditional Execution

Subroutine ์ˆ˜ํ–‰ ํ›„ ์›๋ž˜ ์ฝ”๋“œ๋กœ ๋Œ์•„์˜ฌ ๋•Œ ๋งŽ์ด ์‚ฌ์šฉ.

  • BL SUBR: Branch to SUBR with Link
  • r14 = r15 - 4 (return address ์ €์žฅ) โ†’ PC์— LR์„ ๋ณต์›
  • B SUBR: Branch only (no link)

Nested Call์ผ ๊ฒฝ์šฐ

์œ„์™€ ๊ฐ™์€ ๋ฐฉ๋ฒ•์˜ ๋ฌธ์ œ ๋ฐœ์ƒ โ†’ r14๋ฅผ stack์— pushํ•ด์ค„ ํ•„์š”๊ฐ€ ์žˆ์Œ (subroutine์—์„œ subroutine์„ callํ•  ๊ฒฝ์šฐ).

์˜ˆ:

BL SUB1         ; branch to SUB1, r14 โ† โ–ณ (โ–ณ๋Š” ํ˜„์žฌ PC + #4)
                ; return to here
SUB1 STMFD r13!, {r0-r2, r14}  ; save work & link regs
     BL SUB2    ; r14 โ† โ–ก
     ...
SUB2 ...

โ†’ โ–ณ์„ ๋‹ค ๋ฎ์–ด์“ฐ๊ธฐ์— โ–ณ๋กœ ๋Œ์•„๊ฐˆ ๋ฐฉ๋ฒ•์ด ์—†์Œ!

ํ•ด๊ฒฐ ๋ฐฉ๋ฒ•์œผ๋กœ STMFD I์„ ์ˆ˜ํ–‰ โ†’ r14๋ฅผ stack์— ์ €์žฅํ•˜๊ณ  ๋ฎ์–ด์”€. Full Descending ๋ฐฉ์‹. ๋‚˜์ค‘์— stack์—์„œ ๋‹ค์‹œ ๊บผ๋‚ด์„œ ๋Œ์•„์˜ฌ ์ฃผ์†Œ ๊ฐ€์ ธ์˜ด.

Subroutine Return Instructions

SUB2 ...
     MOV pc, r14    ; copy r14 into r15 to return

BL SUB1
SUB1 STMFD r13!, {r0-r2, r14}   ; save work regs/link โ†’ stack์— r14 ์ €์žฅ
     BL SUB2
     ...
     LDMFD r13!, {r0-r2, pc}    ; restore work regs/link โ†’ ๋‚˜์ค‘์— r14์—์„œ ๊ฐ€์ ธ์˜ด
     ; MOV PC, r14๋ฅผ ์ƒ๋žตํ•˜๊ธฐ ์œ„ํ•ด r14 ๋Œ€์‹  PC๋ฅผ ์”€

Supervisor Calls (Privileged level์—์„œ ๋™์ž‘)

Supervisor: ํŠน๊ถŒ level์—์„œ ๋™์ž‘ํ•˜๋Š” ํ”„๋กœ๊ทธ๋žจ, user level๋ณด๋‹ค ๋†’์€ ์šฐ์„ ์ˆœ์œ„, system level I๋กœ ๊ตฌํ˜„.

SWI (Software Interrupt)

ํŠน๋ณ„ํ•œ subroutine์„ callํ•˜๋Š” I (call ํ•œ device๋ฅผ ์ˆ˜ํ–‰ํ•ด์•ผ ํ•˜๋Š”์ง€ ํ™•์ธํ•˜๋Š” ์ฝ”๋“œ).

์˜ˆ: r0์˜ bottom Byte๋ฅผ display๋กœ ๋ณด๋ƒ„:

SWI SWI_WriteC    ; output r0[7:0] โ†’ r0์˜ ํ•˜์œ„ ์ฒซ Byte ์ถœ๋ ฅ (User level program์ด
                  ; ๋ชจ๋‹ˆํ„ฐ์— ๋Œ€ํ•œ ์ œ์–ด๊ถŒ์„ ๊ฐ€์ง)
  • SWI SWI_Exit โ€” return to monitor (์ œ์–ด๊ถŒํ•œ์„ Monitor๋กœ ๋Œ๋ ค์คŒ)

Branch and Link ๋ฐ Supervisor Calls

๋น„์Šทํ•œ ๊ธ€ ์ถ”์ฒœ

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