5. Cortex-M0

5μž₯ Cortex-M0 κ°œμš”

ARM Cortex-M0λŠ” μ΄ˆμ €μ „λ ₯, μ΄ˆμ†Œν˜• MCUλ₯Ό μœ„ν•œ ARMv6-M μ•„ν‚€ν…μ²˜ 기반 ν”„λ‘œμ„Έμ„œ μ½”μ–΄. 3-stage pipeline, Thumb-only λͺ…λ Ήμ–΄ 지원, μ΅œμ†Œν•œμ˜ NVIC으둜 κ΅¬μ„±λ˜μ–΄ IoT/μ„Όμ„œ λ…Έλ“œ 등에 μ΅œμ ν™”λ˜μ–΄ μžˆλ‹€.

Cortex-M0 νŠΉμ§•

  • ARMv6-M architecture
  • 3-stage pipeline: Fetch β†’ Decode β†’ Execute
  • Thumb instruction set (16-bit) + 일뢀 Thumb-2 (32-bit)
  • ~11,000 gates (Cortex-M3보닀 훨씬 μž‘μŒ)
  • ~12 ΞΌW/MHz μˆ˜μ€€μ˜ μ΄ˆμ €μ „λ ₯
  • Single-cycle multiplier (option)
  • NVIC: Nested Vectored Interrupt Controller (up to 32 interrupts)

Cortex-M0 ꡬ쑰

β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”
β”‚   Cortex-M0 Processor Core          β”‚
β”‚  β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”   β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”   β”‚
β”‚  β”‚ Register β”‚   β”‚  NVIC        β”‚   β”‚
β”‚  β”‚ File     β”‚   β”‚ (up to 32)   β”‚   β”‚
β”‚  β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜   β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜   β”‚
β”‚  β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”   β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”   β”‚
β”‚  β”‚ ALU      β”‚   β”‚  Debug (SWD) β”‚   β”‚
β”‚  β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜   β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜   β”‚
β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜
   AHB-lite bus β†’ Memory, Peripherals

Register Set

  • R0~R12: λ²”μš© register
  • R0~R7: Low registers (λͺ¨λ“  Thumb Iμ—μ„œ 직접 μ‚¬μš©)
  • R8~R12: High registers (μ œν•œμ  μ‚¬μš©, MOV/ADDμ—μ„œλ§Œ)
  • R13: Stack Pointer (MSP / PSP bank)
  • R14: Link Register
  • R15: Program Counter
  • xPSR: Program Status Register

Operating Modes

  • Thread mode: 일반 ν”„λ‘œκ·Έλž¨ μ‹€ν–‰
  • Handler mode: Exception handler μ‹€ν–‰

Privilege:

  • Privileged: λͺ¨λ“  κΈ°λŠ₯ μ ‘κ·Ό κ°€λŠ₯
  • Unprivileged: 일뢀 μ œν•œ (Cortex-M0λŠ” 항상 Privileged)

Memory Map

$2^{32}$ B = 4 GB 가상 μ£Όμ†Œ 곡간:

  • 0x00000000 ~ 0x1FFFFFFF: Code (0.5 GB)
  • 0x20000000 ~ 0x3FFFFFFF: SRAM
  • 0x40000000 ~ 0x5FFFFFFF: Peripheral
  • 0x60000000 ~ 0xDFFFFFFF: External RAM/Device
  • 0xE0000000 ~ 0xE00FFFFF: Private Peripheral Bus (NVIC, SysTick, SCB)

Exception / Interrupt

  • Vector table: 0x00000000에 μœ„μΉ˜
  • 15 system exceptions + μ΅œλŒ€ 32 external IRQs
  • Priority: Reset > NMI > HardFault > configurable

Thumb Instruction Set

Cortex-M0λŠ” Thumb λͺ…λ Ήμ–΄λ§Œ 지원. 일뢀 32-bit Thumb-2 (BL, DSB, DMB, ISB, MRS, MSR λ“±).

  • 16-bit λͺ…λ Ήμ–΄ β†’ μ½”λ“œ 크기 절감
  • Branch, data processing, load/store, control flow

3-Stage Pipeline

[Fetch] β†’ [Decode] β†’ [Execute]
  • Branch prediction μ—†μŒ (M3 μ΄μƒμ—μ„œ λ„μž…)
  • Branch taken β†’ pipeline flush (1 cycle penalty)

SysTick Timer

24-bit down counter둜 κ°„λ‹¨ν•œ time-base 제곡. RTOS μŠ€μΌ€μ€„λŸ¬ tick에 자주 μ‚¬μš©.

Cortex-M0 vs M3/M4

νŠΉμ„± M0 M3 M4
ISA ARMv6-M ARMv7-M ARMv7E-M
Thumb-2 μ œν•œμ  전체 전체 + DSP
FPU X X Option
Bit-band X O O
MPU X Option Option
Pipeline 3-stage 3-stage 3-stage
Gates ~11k ~30k ~50k
Use case μ„Όμ„œ, IoT λ²”μš© MCU DSP, λͺ¨ν„° μ œμ–΄

μ‚¬μš© 예

  • STM32F0 series
  • NXP LPC1100 series
  • Nordic nRF51 series
  • Atmel SAM D20

주둜 배터리 ꡬ동 IoT κΈ°κΈ°, μ„Όμ„œ λ…Έλ“œ, κ°„λ‹¨ν•œ μ œμ–΄κΈ°μ— μ‚¬μš©.

정리

ν•­λͺ© κ°’
Arch ARMv6-M
Pipeline 3-stage
ISA Thumb + subset of Thumb-2
Register R0~R15, xPSR, MSP/PSP
NVIC μ΅œλŒ€ 32 IRQ
Memory 4 GB μ„ ν˜• μ£Όμ†Œ 곡간
μš©λ„ μ €μ „λ ₯ IoT/sensor MCU

Cortex-M0λŠ” κ°€μž₯ μž‘κ³  μ €λ ΄ν•œ ARM core둜, 8-bit MCU μ‹œμž₯을 32-bit둜 λŒ€μ²΄ν•œ 주역이닀.

Cortex-M0 ꡬ쑰 Register Set Memory Map Pipeline 및 NVIC

λΉ„μŠ·ν•œ κΈ€ μΆ”μ²œ

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