5. Cortex-M0
5μ₯ Cortex-M0 κ°μ
ARM Cortex-M0λ μ΄μ μ λ ₯, μ΄μν MCUλ₯Ό μν ARMv6-M μν€ν μ² κΈ°λ° νλ‘μΈμ μ½μ΄. 3-stage pipeline, Thumb-only λͺ λ Ήμ΄ μ§μ, μ΅μνμ NVICμΌλ‘ ꡬμ±λμ΄ IoT/μΌμ λ Έλ λ±μ μ΅μ νλμ΄ μλ€.
Cortex-M0 νΉμ§
- ARMv6-M architecture
- 3-stage pipeline: Fetch β Decode β Execute
- Thumb instruction set (16-bit) + μΌλΆ Thumb-2 (32-bit)
- ~11,000 gates (Cortex-M3λ³΄λ€ ν¨μ¬ μμ)
- ~12 ΞΌW/MHz μμ€μ μ΄μ μ λ ₯
- Single-cycle multiplier (option)
- NVIC: Nested Vectored Interrupt Controller (up to 32 interrupts)
Cortex-M0 ꡬ쑰
ββββββββββββββββββββββββββββββββββββββ
β Cortex-M0 Processor Core β
β ββββββββββββ ββββββββββββββββ β
β β Register β β NVIC β β
β β File β β (up to 32) β β
β ββββββββββββ ββββββββββββββββ β
β ββββββββββββ ββββββββββββββββ β
β β ALU β β Debug (SWD) β β
β ββββββββββββ ββββββββββββββββ β
ββββββββββββββββββββββββββββββββββββββ
AHB-lite bus β Memory, Peripherals
Register Set
- R0~R12: λ²μ© register
- R0~R7: Low registers (λͺ¨λ Thumb Iμμ μ§μ μ¬μ©)
- R8~R12: High registers (μ νμ μ¬μ©, MOV/ADDμμλ§)
- R13: Stack Pointer (MSP / PSP bank)
- R14: Link Register
- R15: Program Counter
- xPSR: Program Status Register
Operating Modes
- Thread mode: μΌλ° νλ‘κ·Έλ¨ μ€ν
- Handler mode: Exception handler μ€ν
Privilege:
- Privileged: λͺ¨λ κΈ°λ₯ μ κ·Ό κ°λ₯
- Unprivileged: μΌλΆ μ ν (Cortex-M0λ νμ Privileged)
Memory Map
$2^{32}$ B = 4 GB κ°μ μ£Όμ 곡κ°:
- 0x00000000 ~ 0x1FFFFFFF: Code (0.5 GB)
- 0x20000000 ~ 0x3FFFFFFF: SRAM
- 0x40000000 ~ 0x5FFFFFFF: Peripheral
- 0x60000000 ~ 0xDFFFFFFF: External RAM/Device
- 0xE0000000 ~ 0xE00FFFFF: Private Peripheral Bus (NVIC, SysTick, SCB)
Exception / Interrupt
- Vector table: 0x00000000μ μμΉ
- 15 system exceptions + μ΅λ 32 external IRQs
- Priority: Reset > NMI > HardFault > configurable
Thumb Instruction Set
Cortex-M0λ Thumb λͺ λ Ήμ΄λ§ μ§μ. μΌλΆ 32-bit Thumb-2 (BL, DSB, DMB, ISB, MRS, MSR λ±).
- 16-bit λͺ λ Ήμ΄ β μ½λ ν¬κΈ° μ κ°
- Branch, data processing, load/store, control flow
3-Stage Pipeline
[Fetch] β [Decode] β [Execute]
- Branch prediction μμ (M3 μ΄μμμ λμ )
- Branch taken β pipeline flush (1 cycle penalty)
SysTick Timer
24-bit down counterλ‘ κ°λ¨ν time-base μ 곡. RTOS μ€μΌμ€λ¬ tickμ μμ£Ό μ¬μ©.
Cortex-M0 vs M3/M4
| νΉμ± | M0 | M3 | M4 |
|---|---|---|---|
| ISA | ARMv6-M | ARMv7-M | ARMv7E-M |
| Thumb-2 | μ νμ | μ 체 | μ 체 + DSP |
| FPU | X | X | Option |
| Bit-band | X | O | O |
| MPU | X | Option | Option |
| Pipeline | 3-stage | 3-stage | 3-stage |
| Gates | ~11k | ~30k | ~50k |
| Use case | μΌμ, IoT | λ²μ© MCU | DSP, λͺ¨ν° μ μ΄ |
μ¬μ© μ
- STM32F0 series
- NXP LPC1100 series
- Nordic nRF51 series
- Atmel SAM D20
μ£Όλ‘ λ°°ν°λ¦¬ ꡬλ IoT κΈ°κΈ°, μΌμ λ Έλ, κ°λ¨ν μ μ΄κΈ°μ μ¬μ©.
μ 리
| νλͺ© | κ° |
|---|---|
| Arch | ARMv6-M |
| Pipeline | 3-stage |
| ISA | Thumb + subset of Thumb-2 |
| Register | R0~R15, xPSR, MSP/PSP |
| NVIC | μ΅λ 32 IRQ |
| Memory | 4 GB μ ν μ£Όμ κ³΅κ° |
| μ©λ | μ μ λ ₯ IoT/sensor MCU |
Cortex-M0λ κ°μ₯ μκ³ μ λ ΄ν ARM coreλ‘, 8-bit MCU μμ₯μ 32-bitλ‘ λ체ν μ£Όμμ΄λ€.

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